1. Field of the Invention
The present invention relates generally to a semiconductor device, and more particularly, to a semiconductor device having a planarized surface. The invention further relates to a method of manufacturing such a semiconductor device.
2. Description of the Background Art
FIG. 22 is a sectional view showing a conventional semiconductor device. At a surface of a silicon substrate 1, an isolation oxide film 2 for isolating an active region from another is formed. In the active region, a field effect transistor (MOSFET) is formed consisting of a gate oxide film 3, a gate 4 of, for example, tungsten silicide, and impurity diffusion layers 6. A first interlayer insulating film 17 is formed by a silicon oxide film 8, a silicon nitride film 9, a BPSG (Boro-Phospho Silicate Glass) film 10 and a silicon oxide film 12. A surface of BPSG film 10 is planarized by heat treatment in oxygen or steam atmosphere. Silicon nitride film 9 is provided so as to prevent oxidation of the underlying silicon substrate 1 and gate 4 during thermal treatment. Silicon oxide film 12 is provided because of the following reason. That is, BPSG film 10 absorbs moisture during manufacturing process, thereby forming phosphoric acid at the surface of BPSG film 10. Silicon oxide film 12 prevents corrosion of a first interconnection layer 15 by the phosphoric acid.
A contact hole is provided in first interlayer insulating film 17. A first plug 14 is formed by filling the contact hole with tungsten or the like. First plug 14 connects impurity diffusion layer 6 or gate 4 and first interconnection layer 15 which will be described later.
First interconnection layer 15 is formed on first interlayer insulating film 17. A second interlayer insulating film 27 is provided to cover first interconnection layer 15. Second interlayer insulating film 27 consists of a silicon oxide film 18 formed by such method as plasma-excited chemical vapor deposition (plasma CVD) or Spin-On-Glass (SOG). A through-hole is formed in second interlayer insulating film 27. A second plug 24 is filled in the through-hole. Second plug 24 connects first interconnection layer 15 and a second interconnection layer 25.
By using a similar method, second interconnection layer 25, a third interlayer insulating film 37, a third plug 34, a third interconnection layer 35, a fourth interlayer insulating film 47, a fourth plug 44, and a fourth interconnection layer 45 are formed. A protection film 46 consisting of a silicon nitride film or the like which is formed by plasma CVD is formed as an uppermost layer.
The above-described semiconductor device includes MOSFET and four layers of interconnections. If an interlayer insulating film is formed by a conventional method (such as SOG), a stepped portion can locally be planarized. However, in a region where a difference in level exceeds 10 .mu.m, the difference cannot be reduced. Therefore, a stepped portion is generated between a region having many layers of interconnections and a region having no interconnection. Upper layers have greater difference in level.
The greater difference in level gives rise to the following problem. A small pattern must be formed by photolithography in order to enhance integration level of a semiconductor device. A small pattern can be formed by, for example, using an optical system which has a high numerical aperture (NA), or by performing exposure with light having a short wavelength. In any of the methods, however, there is a drawback that the depth of focus will be shorter. Therefore, it is impossible to make a small pattern at a plane where a great difference in level exists. Consequently, pitch between wires must be made larger at upper interconnection layers, making it eventually difficult to enhance integration level.
In order to solve the above-described problem, a method for planarizing a surface of a semiconductor device is proposed (in Japanese Patent Laying-Open No. 5-30052) in which a convex portion of an interlayer insulating film is selectively removed by Chemical/Mechanical Polishing (CMP).
FIG. 23 shows the concept of CMP method. A polishing cloth 62 is provided on a polishing board 61. Polishing cloth 62 is made of polyurethane. Polishing agent 64 is supplied to polishing cloth 62 from a tube 65. Polishing agent 64 is prepared by suspending particles of silica (SiO.sub.2) with a diameter of approximately 0.01 .mu.m in alkalescent liquid. A semiconductor wafer 63 is pressed by a supporting rod 168 toward polishing board 61 so that its surface contacts polishing cloth 62. By rotating polishing board 61 and supporting rod 168 while supplying polishing agent 64 to polishing cloth 62, the surface of semiconductor wafer 63 is polished chemically and mechanically.
FIG. 24 is a cross sectional view of a semiconductor device having an interlayer insulating film planarized by CMP method. By this method as well, a stepped portion is generated between a region 16 which is wide and having a high density of interconnections and a region 26 having a low density of interconnections.
The reason for the generation of such a stepped portion will be described below with reference to FIG. 24. In region 16 having a high interconnection density, when interlayer insulating film 27 is formed on interconnections, a gap between interconnections 15 is filled with interlayer insulating film 27, thereby forming a convex pattern 83 spreading horizontally on a large scale. On the other hand, in region 26 having a low interconnection density, a gap between interconnections 15 is not completely filled. Therefore, even after the formation of interlayer insulating film 27, a concave portion 84 reflecting the shape of the pattern corresponding to the interconnection layers 15 is formed at a surface of interlayer insulating film 27.
A study has been conducted as to the dependency of the degree of planarization in CMP method. The result is as follows.
FIG. 25 is a plan view of a semiconductor wafer. Approximately one hundred chips 67 are formed on the semiconductor wafer 63. FIG. 26 is an enlarged view of chip 67. A convex portion 90 is formed on chip 67. The two-dimensional shape of convex portion 90 is substantially a quadrangle having longer and shorter sides 69 and 70. As a result of the study, it has been found that the degree of planarization obtained in CMP method depends on a length of shorter side 70 of convex portion 90; a convex portion 90 of which shorter side 70 is rather long is generally hard to planarize. This will be explained later in detail.
Referring to FIG. 27A, the ratio (H/H.sub.0) between the height (H.sub.0) of an initial convex portion 90 and the height (H) of a polished convex portion 71 is defined herein as a relative difference in level. FIG. 27B is a plan view of FIG. 27A. Referring to FIG. 27B, the two-dimensional shape of the unpolished convex portion 90 is substantially a quadrangle including longer and shorter sides 69 and 70.
FIG. 28 shows the relation between the relative difference in level (H/H.sub.0) and polishing amount on the planarized portion regarding convex portion 90 of various sizes.
Referring to FIG. 27B and FIG. 28, straight lines 71 through 75 show the data obtained when the length of shorter side 70 of convex portion 90 is 20 .mu.m, 150 .mu.m, 300 .mu.m, 500 .mu.m, and 1.2 mm, respectively.
Referring to FIG. 28, the relative difference in level decreases exponentially as a function of the polishing amount on the planarized portion. Regarding the convex portion of which shorter side is rather long, however, the straight line is less inclined (see straight line 75). It has been empirically recognized that the relation between the polishing amount R on the planarized portion and the relative difference in level (H/H.sub.0) can be expressed by the following empirical formula. EQU H/H.sub.0 =exp(-R/R.sub.0)
wherein R.sub.0 is a constant. It has been found that there is correlation as shown in FIG. 29A between the length of shorter side 70 of convex portion 90 and the polishing amount R required for making 1/e the relative difference in level (H/H.sub.0). FIG. 29B shows the relation between the length of longer side 69 of convex portion 90 and the polishing amount R required for making 1/e the relative difference in level (H/H.sub.0). It has been learned that there is no correlation between the two. FIG. 29C shows the relation between plane area (longer side 69 x shorter side 70) of convex portion 90 and the polishing amount R required for making 1/e the relative difference in level. There has been no correlation found between the two.
In an actual semiconductor device, a portion corresponding to a memory device or the like is formed by a pattern having a high density of interconnections, and this portion providing a convex pattern 83 spreading horizontally on a large scale (see FIG. 24). The length of shorter side 70 of such convex pattern 83 sometimes exceeds 1 mm, and it is likely to be longer in the future. If such convex pattern 83 spreading horizontally on a large scale is planarized only by CMP, the polishing amount of 1 .mu.m or more is required on the planarized portion, as shown in FIG. 29A. However, uniformity of thickness of a film formed on the wafer considerably degrades as polishing amount increases. In order to maintain the uniformity of the thickness of the film, the maximum polishing amount on the planarized portion is approximately 0.5 .mu.m.
Avanzino et al. proposes a method to avoid the above-mentioned problem (in U.S. Pat. No. 4,954,459).
FIGS. 30-33 are partial cross sectional views showing in order respective steps in a method disclosed in U.S. Pat. No. 4,954,459 for completely planarizing a convex pattern by CMP.
Referring to FIG. 30, a raised portion 81 is formed on a substrate 1. An insulating film 82 is formed on substrate 1, covering raised portion 81. A surface of insulating film 82 protrudes on raised portion 81 and sinks between raised portions 81. A resist pattern 86, having an opening portion 85 on the protruded portion of insulating film 82 (hereinafter referred to as a convex portion 91), is formed on insulating film 82.
Referring to FIGS. 30 and 31, convex portion 91 of insulating film 82 is etched using resist pattern 86 as a mask.
Referring to FIGS. 31 and 32, resist pattern 86 is removed. Referring to FIG. 33, the surface of insulating film 82 is planarized by CMP.
A first problem of the above-mentioned method disclosed in U.S. Pat. No. 4,954,459 is that resist pattern 86 cannot be formed satisfactorily. If a resist pattern is to be formed on insulating film 82 covering raised portion 81 as illustrated in FIG. 34A, the resist pattern 86 to be formed then has a shape shown in FIG. 34B.
Consequently, the first problem is that resist pattern 86 falls down or disappears during developing or etching process if a width W of resist pattern 86 is, for example, 0.4 .mu.m or less.
FIGS. 35A-35C illustrates a second problem. Like or corresponding elements in FIGS. 35A-35C are denoted by like reference numerals in FIG. 34, and a description thereof will therefore not be repeated. The second problem is that opening portion 85 may be displaced when it is formed, as illustrated in FIG. 35A, because of misalignment of a mask for forming resist pattern 86. There is another problem that diameter of opening portion 85 varies in size.
If etching is performed in such a situation, a recess 87 is generated.
Resist pattern 86 is then removed, and the surface of insulating film 82 is planarized by CMP. As a result, recess 87 remains at the surface of insulating film 82 even after planarizing process.
Therefore, a surface of a semiconductor device cannot be completely planarized by the method disclosed in the above-mentioned U.S. Pat. No. 4,954,459 either. Accordingly, the difference in level cannot be reduced by any of the conventional methods, making it difficult to minituarize semiconductor device having a structure of multi-layered interconnections.
Even if the difference in level at the convex pattern spreading horizontally on a large scale could be reduced by a conventional CMP method, the required polishing amount is greater. As a result, thickness of the film becomes uneven after it is polished, leading to a drop in yield. The method gives rise to another problem of a decrease in productivity because it requires a long time for polishing.